Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration

Owning a high-end semiconductor foundry is luxury very few companies can afford. Thus, fabless design outsource integrated circuit fabrication to third parties. Within foundries, rogue elements may gain access the customer’s layout and perform malicious acts, including insertion of hardware trojan (HT). Many works focus on structure/effects HT, while have demonstrated viability their HTs in silicon. Even fewer disclose how are inserted or time required for this activity. Our work details, first time, effortlessly HT be into finalized by presenting an framework based engineering change order flow. For validation, we built ASIC prototype 65nm CMOS technology comprising four trojaned cryptocores. A side-channel each core with intent leaking cryptokey over power channel. Moreover, determined that entire attack mounted little one hour. We also show was successful all tested samples. Finally, our measurements demonstrate robustness SCT against skews manufacturing process.